In various memory systems a controller stores data in multiple memory devices. Storage operations that access multiple memory devices in parallel may cause a peak of current and power consumption in the memory system.
Methods for controlling the peak current or peak power in multi-memory systems are known in the art. For example, U.S. Patent Application Publication 2015/0205540, whose disclosure is incorporated herein by reference, describes a memory system that includes nonvolatile memory devices (NVMs) connected to a controller via a channel. The memory devices are provided with data according to an interleaving approach. The controller respectively accesses the NVMs and determines a number of program operations that may be simultaneously executed by the NVMs in conjunction with an additional operation upon comparing a peak operating current associated with a sum of respective peak operating currents for the number of program operations and the at least one additional operation with a reference peak current.
U.S. Pat. No. 8,432,738, whose disclosure is incorporated herein by reference, describes a system and a method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.